The field of the invention relates to memory devices and more particularly to non-volatile semiconductor memories.
Continuing to increase rapidly is the use of computer memory, in particular non-volatile semiconductor memory, which retains its stored information even when power is removed. A wide variety of non-volatile memories exist. A typical commercial form of non-volatile memory utilizes one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data.
Non-volatile memory is unlike volatile random access memory (“RAM”), which is also solid-state memory, but does not retain its stored data after power is removed. The ability to retain data without a constant source of power makes non-volatile memory well adapted for consumer devices. Such memories are well adapted to small, portable devices because they are typically relatively small, have low power consumption, operate quickly, and are relatively immune to the operating environment.
In general, the small size, low power consumption, high speed and immunity to environment are derived from the structure of the memory. In this regard, such non-volatile memory devices are typically fabricated on silicon substrates. In addition, to obtain the advantages of small size, etc., and well as reduce costs, there is a continual effort to fabricate more circuitry within a given area.
Highly effective approaches to increase density of nonvolatile memory include monolithic three dimensional memories disclosed in Johnson et al. U.S. Pat. No. 6,034,882, Johnson et al. U.S. Pat. No. 6,525,953, Knall et al. U.S. Pat. No. 6,420,215, and Vyvoda et al. U.S. Pat. No. 6,952,043, all hereby incorporated by reference in the entirety for all purposes.
The fabrication of these high-density, three dimensional memory arrays presents a number of challenges. For instance, misalignment of features during fabrication results in reduced yield and becomes more problematic as feature size is reduced. For example, in the event that a photomask is improperly placed, a memory element may be short circuited during subsequent fabrication operations. Thus, alternate methods of fabrication are needed that reduce the difficulties of aligning memory elements during fabrication while permitting improved density, decreased future size, and improved yield.